#this is a Makefile

#this is a comment in a Makefile

#the following are macros
#they can also be passed on the command line, by typing, say, "make CC=cc life"
CC = gcc
CFLAGS = -O2 -Wall -I../include
CLIBS = -L../lib -lm -ldl
RM = rm -i
SOURCES = life.c helper.c
OBJS = $(SOURCES:.c=.o)

#target:	dependencies
#		actions

life:	$(OBJS)
	$(CC) $(CFLAGS) life.o helper.o -o $@ $(CLIBS)
#the first target is also the default target (if you just type "make")

life.o:	life.c life.h
	@echo the following files have changed: $?
	$(CC) $(CFLAGS) -c life.c
# '@' as the first character stops the command from being displayed

helper.o:	helper.c helper.h
	$(CC) $(CFLAGS) -c helper.c

.SUFFIXES:	.c .o .i .java .class

.c.i:
	@echo I am preprocessing the file $< into $@
	/usr/ccs/lib/cpp $< > $@

.c.o:
	$(CC) $(CFLAGS) -c $<

.c:
	$(CC) $(CFLAGS) $< -o $@ $(CLIBS)

.java.class:
	javac $< > $@

#make can also be used for things other than compiling:

run:	life
	./life r=24 c=80 glider &

show:
	ps -ef | grep life | grep -v grep

stop:
	kill `ps -defac | grep life | grep -v grep | awk '{print $$2}'`

clean:
	echo "I'm nuking all object files!"
	$(RM) *.o life

backup:
	cp *.[ch] ./bakup/

restore:	clean
	cp ./backup/* .